Voltage level shifting circuits are well known in the art for translating, or converting, digital signals driven with a first set of voltage supplies to a signal driven with a second set of voltage supplies, where the high (or low) voltage output is higher (or lower) than that in the first set of voltage supplies. Voltage level shifting is used in systems where circuits operating with different voltage supplies must communicate with each other.
Those of skill in the art will understand that dynamic random access memory (DRAM) conventionally employs level shifters in the wordline driver circuits of a memory array. The wordline driver circuits in a memory with n-channel cell transistors preferably drive wordlines with a voltage above the logic ‘1’ power supply voltage (typically VDD) to maximize the charge written into and read out from accessed DRAM cells. The wordlines can further be driven to a voltage level below VSS to minimize leakage current from the DRAM cells.
FIG. 1 is a circuit schematic including a level shifter circuit of the prior art that is used to drive wordlines in a DRAM to voltage levels above VDD and below VSS. FIG. 1 includes a logic circuit 12, and a level shifter circuit 10 comprised of n-channel pass transistor 14, p-channel pass transistor 16, cross-coupled p-channel transistors 18 and 20, and cross-coupled n-channel transistors 22 and 24.
Logic circuit 12 is shown as an NAND gate for receiving any number and combination of address signals and control signals, and for providing a single decoded output. Logic circuit 12 is powered by VDD and VSS voltage supplies, and can have any known circuit configuration. The output of logic circuit 12 is split in parallel and passed through n-channel pass transistor 14 and p-channel pass transistor 16. Pass transistor 14 has its gate tied to VDD to isolate logic circuit 12 from voltage VPP (above VDD), while pass transistor 16 has its gate tied to VSS to isolate logic circuit 12 from the negative voltage VBB (below VSS). The drain of transistor 16 is connected to the gate of transistor 24 and the drain of transistor 22. The drain of transistor 14 is connected to the gate of transistor 20 and the drain of transistor 18. Thus when the output of the logic circuit 12 is VDD, that VDD level is passed through transistor 16 to the cross-coupled transistors 22 and 24 such that transistor 24 is on and transistor 22 is off. In parallel, transistor 20 is off and transistor 18 is on and the wordline is at VBB.
When the output of the logic circuit 12 changes from VDD to VSS, that VSS level is passed through transistor 14 to the cross-coupled transistors 18 and 20 such that transistor 20 begins to turn on and transistor 18 begins to turn off. In parallel, the rising wordline voltage turns on transistor 22, which causes cross-coupled transistor 24 to be turned off. The size of the pull down logic of gate 12 and the size of transistor 14 must be large enough to provide enough current to counteract the pull-up current of transistor 18 on the gate of transistor 20. Similarly, the size of the pull up logic of gate 12 and the size of transistor 16 must be large enough to provide enough current to counteract the pull-down of transistor 22 on the gate of transistor 24 when the output of logic gate 12 changes from VSS to VDD. As transistors 20 and 24 are connected directly to the wordline, their sizes must be large enough to drive the wordline in a timely manner. The other transistors in the level shift circuit 10 and the logic gate 12 must also be sized large enough so that the level shift circuit 10 operates correctly. Thus logic gate 12 and level shift circuit 10 may require a relatively large area.
Furthermore, when the wordline voltage is switching from VBB to VPP or from VPP to VBB, crowbar current will occur in transistors 20 and 24 as there is a direct current path from VPP to VBB for a brief period of time.
The operation of the level shifter 10 can be enhanced if pass transistors 14 and 16 are fabricated with low threshold voltages. However, since current leakage is a growing problem in small geometry semiconductor processes, this solution may not be available for low power processes where only high Vt devices can be fabricated.
A second prior art circuit for translating a VDD/VSS logic signal to a VPP/VBB level wordline signal is shown in FIG. 2. The circuit in FIG. 2 includes a logic circuit 32, a level shift circuit 30 to shift the VDD/VSS level output of logic circuit 32 to VPP/VSS, a level shift circuit 31 to shift the VDD/VSS level output of logic circuit 32 to VDD/VBB, and wordline drive transistors 42 and 50. This circuit differs from the circuit in FIG. 1 in that the wordline drive transistors 42 and 50 are not part of the level shift circuitry, and that there are two separate, independent level shifters used to control the gates of wordline drive transistors 42 and 50. Since an extra stage is included in the circuit in FIG. 2, the level shift circuitry 31 and 30 and logic circuitry 32 can use smaller device sizes than the logic gate circuit 12 and level shift circuit 10 in FIG. 1. However, the size of the series connection of the pull-down in logic gate 32 and the pass device 34 must be large enough to overcome the pull-up current of transistor 38. Similarly, the size of the series connection of the pull-up in logic gate 32 and the pass device 36 must be large enough to overcome the pull-down current of transistor 52.
Crowbar current is also a concern in level shift circuits. Smaller device sizes in level shift circuitry also result in lower crowbar current consumption. The device sizes of the level shift circuits 30 and 31 in FIG. 2 can be smaller than the device sizes in the level shifter in FIG. 1, and thus contribute smaller crowbar current; however there are two level shift circuits. In addition, crowbar current will occur between devices 42 and 50.
As can be understood by any person skilled in the art, the loading of the logic circuit responsible for changing the state of the level shift circuit can affect wordline activation performance. Preferably, the wordlines are activated quickly in response to a decoded row address and/or control signal. Additionally, a larger load on that same logic circuit can require the use of larger device sizes in both the logic circuit and level shifter, increasing the area required. The additional cost of a multiple Vt fabrication process which might enable smaller device sizes may not be acceptable either. Minimizing crowbar current is also a concern in level shift circuits.
Accordingly, there is a need for a circuit to level shift a VDD/VSS logic signal to a VPP/VBB signal, where the level shift circuitry places minimal loading on the preceding logic circuit, occupies a small area and minimizes the crowbar currents.